T1C: Open-Source AI Accelerator
T1C (Tier 1 Chip)
The first honest, physics-verified, and fully open-source AI accelerator. Released under MIT license by Alexzo, founded by Sarthak.
D-IMC Architecture
Digital In-Memory Computing (D-IMC) eliminates the data movement bottleneck by computing directly inside memory.
Hardware MIM
Multi-Instance MAAU provides hardware-level tenant isolation, inspired by NVIDIA MIG but fully open-source.
MIT Open Source
Full RTL, GDSII, and PCB files are released under MIT license. Anyone can build, modify, and improve.
Linear Scaling
Modular blade design allows for seamless scaling from a single $280 blade to massive compute clusters.
Honest Specifications
Physics-verified performance. No hidden specs. No fake claims.
| Feature | Verified Spec |
|---|---|
| Process Node | 65nm LP (GF) / 130nm (IHP) |
| Architecture | Digital In-Memory Computing |
| INT4 Performance | 200–400 GFLOPS (Per MAAU) |
| Memory Bandwidth | 168 GB/s (LPDDR5X Wide-Bus) |
| Voltage Stability | ±3mV (5-Layer Adaptive AVS) |
| Hardware Isolation | MIM-4 (Up to 4 Tenants per Chip) |
"We Design It. World Builds It."
T1C does for AI chips what RISC-V did for CPUs—it provides a complete, honest, and physics-verified architecture that anyone can fabricate, modify, and build products on.
Digital In-Memory Computing
Computations happen near memory, not in a distant processor. This eliminates the Von Neumann bottleneck that slows down every conventional AI chip.
Community-Driven Future
From 65nm LP shuttle programs to 130nm IHP free research runs, T1C is designed for builders who want full RTL and GDSII transparency.
Production Documentation
For a deep-dive into the technical specifications, 5-layer AVS system, TurboQuant technology, and full BOM costs, read our detailed guide.